AMD’s Newest Patent Filing Reveals Unique “Chip Stacking” Method, Significantly Scaling Up Die Usage
AMD's newest patent filing has revealed that the firm is looking towards adopting "multi-chip stacking" in its future Ryzen SoCs, leading towards die scalability.
AMD Might Implement "Overlapped" Chip Stacking, Using Smaller Chiplets Underneath A Larger Die, All In A Single Package
Team Red is always in pursuit of innovating its existing consumer CPU lineup, as the firm is the first manufacturer to introduce a dedicated "3D V-Cache" tile to its processors, known as the "X3D" lineup.
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Now, according to a new patent filing (via @coreteks), it is being said that AMD is reportedly exploring a "novel packaging design", which is said to innovate the chip stacking process, ultimately reducing interconnect delays, and bringing in significant performance uplifts.
The above patent states that AMD plans to adopt an innovative approach to chip stacking, where smaller chiplets are partially overlapped with a larger die. This technique aims at scaling up chip designs by creating room for more additional chiplets, hence more functions on a single die, which will ultimately utilize the contact area much more effectively. Through this, with the same die size, AMD can manage to incorporate higher core counts, larger caches, and more memory bandwidth, which allow them to scale up performance massively.
Another interesting fact about this approach is that Team Red will be able to reduce interconnect latency with such a method, given that overlapping chiplets can reduce the distance between components, leading to faster communication. And, power gating won't be much of an issue with this arrangement too, as segregated chiplets allow for more effective control of individual units.
It won't be wrong to say AMD is indeed a pioneer in adopting a "multi-chiplet" approach, not just for its processors, but GPUs as well. In a previous post, we reported on how Team Red is
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