New details of TSMC's next-gen N2 chip tech aren't totally stellar but could provide a roadmap for new GPUs right through to 2031

pcgamer.com:

Everyone's favorite uber chip foundry TSMC has been dishing the deets on its next-gen node, known as N2 (via Tom's Hardware). And the take home is that its both more efficient and more dense than TSMC's current N3 tech, but perhaps not dramatically so.

Still, the good news is that still gives us at least two generations of GPUs on new silicon nodes to look forward to. That's because current GPUs are all based on derivations on TSMC's N5 silicon.

So, you would expect both AMD and Nvidia (and Intel if they're still in the GPU game) to move to TSMC's current cutting edge chip manufacturing process, N3, at some point, followed by N2. All of which means there's decent scope for progress on the pure process side of things for some time to come.

Indeed, prevailing rumors suggest both of AMD and Nvidia's next-gen graphics chips, including the likes of the mooted Nvidia RTX 5090 and its Blackwell siblings, will remain on N5-derived silicon (likely to be branded N4). That means N2 provides an upgrade path several years down the road.

Anywho, what of the specifics of N2? In terms of density, TSMC is only claiming 1.15x progress over N3, or just 15%. That means TSMC will be able to pack in 15% more transistors per unit of chip area compared to N3.

That's a pretty modest step for a new node. However, it's worth bearing in mind two things.

First, given that's the improvement over N3, the overall increase in density versus today's N5/4 based GPUs will be pretty substantial.

Keep up to date with the most important stories and the best deals, as picked by the PC Gamer team.

What's more, TSMC is claiming improved SRAM density for N2. SRAM density scaling has hit a bit of a wall of late, with TSMC claiming no improvements in that regard for N3 over N5. However, N2 is claimed to achieve 38Mb/mm^2 to N3's 33.55 Mb/mm^2, which is a decent step.

Long story short, SRAM takes up a fair bit of space on most chips, so the inability to shrink SRAM cells was becoming an increasing problem. N2