Pixel 10 Lineup Once Again Rumored To Feature 3nm SoC, With Google Possibly Working Closely With TSMC With The Rumored Expansion Of Its Taiwanese R&D Facility

wccftech.com:

Google is expected to unveil the Tensor G4 later this year for the Pixel 9 lineup, and just like its previous releases, the company is likely sticking with Samsung as its foundry partner. However, next year, the advertising giant is said to take a different direction, with its Pixel 10 range apparently featuring a 3nm SoC from TSMC. To help with the transition, Google is rumored to have expanded its Taiwanese R&D center, where it is expected to collaborate closely with the semiconductor giant to produce its best silicon to date.

Tensor G5 will most likely be the chipset fueling the Pixel 10’s innards; early rumor claimed that TSMC’s second-generation 3nm process will be utilized

The Tensor G3 proves that Google lags behind its competition severely, and a switch from Samsung to TSMC may help matters, allowing the Pixel 10 family to showcase its capabilities on an equal playing field. To expedite the process of introducing its first 3nm chipset, which could be named the Tensor G5, @Revegnus1 has put out a post saying that Google has expanded its R&D facility based in Taiwan. The Mountain View firm is said to be hiring local semiconductor talent, which is likely to boost its in-house silicon efforts.

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While the chipset’s exact name is not mentioned, the rumor does state that the Pixel 10 models will feature a 3nm SoC, suggesting that it is the Tensor G5. Earlier, we reported about a separate rumor, discussing that Google would take advantage of TSMC’s 3nm ‘N3E’ process for its cutting-edge chipset. For those that do not know, the ‘N3E’ node is also known as TSMC’s second-generation 3nm technology and is the same one used for Apple’s M4 that powers the latest family of iPad Pro models.

Expanding its foothold in Taiwan would probably give Google a direct collaboration opportunity with TSMC, with the latter’s engineering talent possibly engaged in optimizing the Tensor G5’s