TSMC Aims To Integrate Over 1 Trillion Transistors In 3D-Packaged & 200 Billion Transistors In Monolithic Chips By 2030

wccftech.com:

TSMC has outlined plans to offer over 1 Trillion transistors in 3D-packaged and 200 Billion in monolithic chips by 2030.

During the IEDM 2023 conference, TSMC showed a roadmap of what the company expects its semiconductor "portfolio" to be shaped like, and it looks like the Taiwanese giant has some ambitious plans for the end of this decade.

Based on the roadmap revealed, TSMC is confident that its processes are on track, with the debut of TSMC's N2 and N2P processes within the 2025-2027 period, while cutting-edge A10 (1nm) and A14 (1.4nm) processes, scheduled for the 2027-2030 timeframe. Apart from process shrinking, TSMC plans on making huge strides in other semiconductor technologies as well, setting a benchmark for the industry to follow.

However, the more interesting part here is that the Taiwan giant has disclosed advancements in two key sectors of the semiconductor industry, which are monolithic designs and 3D Hetero Integration (or in simple terms chiplet designs). The industry is indeed shifting towards chiplet configurations as they offer modularity and cost advantages.

AMD has been leveraging TSMC's chiplet designs for its latest consumer, data center, and now the most recent MI300 accelerator chips. Intel also released its Meteor Lake chips which are the blue team's first chiplet-design for consumer platforms, hinting at the fact that chiplets are the future, with TSMC one step ahead. Intel itself uses chips fabricated on TSMC's process technologies to power Meteor Lake. The company projects 3D Hetero Integration to reach a whopping "one trillion transistors" by 2030.

TSMC doesn't look to stop focusing on monolithic configurations, as just recently, the debut of NVIDIA's Hopper H100 GPUs saw a huge uplift when it