While Intel has been busy making bets on its 18A node as part of its accelerated roadmap towards chip making dominance, TSMC appears to have been beavering away in the background to undercut it.
It's just announced its own «angstrom-class» process, A16, which thanks to its backside power delivery implementation looks set to not only offer significantly improved performance compared to its upcoming NP2 process, but also improve energy efficiency, too. Intel has its own competing backside power delivery tech, PowerVia. While Intel says it will begin producing chips on 18A next year, it doesn't expect to start producing large volumes of chips on the 18A node until 2027.
TSMC says that chips built on the new A16 process will provide an 8-10% speed improvement over N2P at the same voltage, with a 15-20% power reduction at the same speed and up to a 1.10X chip density improvement for data centre products. The company aims to begin production on chips using the tech in 2026.
The A16 process will make use of gate-all-around (GAAFET) nanosheet transistors alongside a backside power rail method called «Super Power Rail», which should not only improve power delivery but also increase transistor density (via Anandtech). Not only that, but TSMC has also indicated that it won't be using ASML's High NA EUV photolithography machines, which strikes as a bit of a «yah boo sucks to be you» given that Intel's been proudly showing off its new machine very recently.
So, it seems like TSMC has reason to be rather pleased with itself. While Intel has been busy securing billions in CHIPS act subsidies in an effort to ensure it can keep up with the developmental pace, TSMC appears to have been creating a new ultra high-tech node of its own, and it looks set to hit Intel right where it hurts. TSMC has already reported strong profits in the first quarter of this year, while Intel has recently reported that its foundry service was running with operating losses of $7 billion in 2023, which
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