TSMC makes the world's graphics chips and predicts 'within a decade a multichiplet GPU will have more than 1 trillion transistors'

pcgamer.com:

Graphics processing units (GPUs) are some of the largest chips made, and in just over a decade, the most powerful graphics processors have gone from comprising a few billion transistors to over 100. But even those figures will be tiny compared to what lies ahead in the future, according to TSMC, and it's explained how it plans to continue making them ever bigger. Billions? Uh uh—how about a cool one trillion transistors?

Taiwan Semiconductor Manufacturing Company (TSMC) is the largest manufacturer of graphics processing units in the world. AMD, Intel, Nvidia, Qualcomm, Tesla, and others are all developing ever larger and more powerful chips. With the likes of Nvidia's recent Blackwell B200, we're already ready past the 100 billion transistor mark and GPUs of the future will need to have far more than this to keep improving the performance and capabilities.

However, fabricating them is becoming increasingly more challenging, as certain elements (such as SRAM bit cells for cache) aren't much smaller than they were five years ago. While logic circuits can still be made smaller, the overall size of the chip dies will just end up getting larger due to the constraints in the other areas. Unfortunately, the maximum size of a single die is pretty much at a limit, too, with the biggest area achievable being a little over 800 square millimetres.

This is known as the reticle limit and there's no sign of this being hugely improved, without costs spiralling. But we've already seen the solution to all of this and in an article for IEEE Spectrum, via The Register, Mark Liu (TSMC's Chairman) and Professor H.-S. Philip Wong (TSMC's Chief Scientist) explain how going down the route of chiplets/tile and 3D stacking will soon make 100 billion transistor GPUs look like nothing.

«The continuation of the trend of increasing transistor count will require multiple chips, interconnected with 2.5D or 3D integration, to perform the computation. The integration of multiple chips, either by