Qualcomm and Google have partne red to develop a RISC-V wearable solution for use with smart watches based on the Wear OS by Google.
The companies announced an expansion of their partnership to develop the tech based on RISC-V, a relatively new chip architecture based on an open standard in competition with rivals such as the Arm architecture.
RISC-V, a royalty-free open-standard instruction set architecture (ISA), allows companies to develop custom cores, fostering innovation and competition in the marketplace. Its openness, flexibility, and scalability benefit the entire value chain, from silicon vendors to OEMs, end devices, and consumers.
This collaboration aims to reduce time to market for original equipment manufacturers (OEMs) looking to launch smartwatches with advanced features such as custom cores, low power consumption, and higher performance. The companies will continue to invest in Snapdragon Wear platforms, solidifying Qualcomm’s position as the leading smartwatch silicon provider for the Wear OS ecosystem.
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Qualcomm senior vice president of product management Ziad Asghar explained in an interview with VentureBeat how the company is thinking about RISC-V technology.
“At a very high level, we’re at a very good inflection point when it comes to the RISC-V instruction set architecture (ISA) as it is becoming an option for multiple industries as something that multiple different vendors in the market can start to use,” Asghar said. “There’s huge amount of momentum behind it. People are seeing the great value
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