AMD Next-Gen Zen 5 CPUs Rumored To Feature Reworked Cache Design, Larger L2 Cache Per Core
AMD Zen 5 core architecture is rumored to feature a fully reworked cache design which will assist with increasing the IPC for next-gen CPUs.
The rumor comes from AdoredTV who has shared the latest information regarding AMD's next-gen Zen 5 architecture. Although AMD isn't quite done yet with its Zen 4 architecture, the company has the first Zen 5 samples already in labs in early prototypes.
The AMD Zen 5 core architecture which is internally codenamed "Nirvana" has had work started on it since 2020-2021. The first Zen 5 products are expected to land in 2024 & based on recent reports, it will be built completely from the ground up. Since it is a completely new design, the internal CPU architecture is bound to see some major changes, and some possible changes are detailed by tech outlet, AdoredTV.
The first major change rumored for AMD's Zen 5 CPU core architecture is the use of a new "Ladder" shared cache. The earlier Zen architectures had the L3 cache split into two 16 MB blocks shared by the two CCX's within each CCD. Each CCX could only access 16 MB of L3 cache pools.
With Zen 3, AMD change this and dropped the dual CCX to a singular CCX which featured a shared 32 MB L3 cache pool that was connected to all 8 cores within the die in a ring configuration. AMD kept the same design on the Zen 4 chips but with Zen 5, this is rumored to change once again to a new 32 MB L3 "Ladder' cache. This structure is said to drastically reduce the inter-core latency and communication bottlenecks compared to the ring interconnect design. Now the figure shown here is just to provide a visual perspective of how the new L3 cache structure would work & we cannot say for sure if the L3 cache will stick to 32 MB or get a boost.
What is rumored to
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