AMD Strix Halo Render Reveals Powerful Ryzen APU Design: 16 Zen 5 Cores, 40 RDNA 3+ GPU Cores, 64 MB L3 Cache
AMD's Strix Halo, the higher-end Ryzen APU, which will power enthusiast laptops with up to 16 Zen 5 cores & 40 RDNA 3+ GPU cores has been revealed in a render diagram published by @Olrak_29.
AMD Strix Halo Render Reveals High-End Chiplet-Based Ryzen APU With Up To 16 Zen 5 CPU Cores & 40 RDNA 3+ GPU Cores
The AMD Strix Halo APUs will be the chiplet offerings, utilizing up to 3 dies, 2 CCDs, and 1 GCD. The chips will feature up to 16 Zen 5 cores with 32 threads. These chips will retain the same L1 and L2 cache structure so that's a maximum of 16 MB L2 cache while the L3 cache will be increased to 32 MB per CCD. So we can see up to 64 MB of L3 cache on the top (two CCD) chips. The CCDs are said to be different than the ones used on Granite Ridge. Also, only the GCD is mentioned which means that there might be no IOD on board the package.
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In fact, based on the render diagram, the AMD Strix Halo APU will incorporate all of the I/O blocks within the GCD which is the largest of the three dies. It will contain an XDNA 2 AI NPU with over 40 TOPs, 32 MB of Infinity Cache, 256-bit LPDDR5X memory and it looks like there will also be Zen 5 LP (Low-Power) cores onboard this die. The GCD/IOD will be connected to the dual Zen 5 CCDs using an Infinity Fabric interconnect.
For the iGPU side, the Strix Halo APUs will retain the RDNA 3+ graphics architecture but will come equipped with 20 WGPs or 40 Compute units. Additionally, to support such high-end iGPUs on a chiplet design, there will also be an additional 32 MB of MALL cache onboard the IOD that will be eliminating bandwidth bottlenecks for this uber iGPU.
Other specifications include support for up to LPDDR5x-8000 (256-bit) memory, and an AI "XDNA 2" NPU capable of delivering over 70 TOPs. The Strix Halo APUs will be centered around the latest FP11 platforms. These APUs will feature TDPs of 70W (cTDP 55W) and will support peak ratings of up to
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