Apple reportedly has plans to unveil the A17 Bionic and the M3 later this year, making both the world’s and TSMC’s first 3nm chips to be found in consumer electronics. Unfortunately, if a new report is to be believed, the Taiwanese manufacturer is struggling to make enough chips to meet Apple’s demand. Here, we discuss what problems the supply chain partner is facing.
TSMC has been unable to ramp up volume production of its 3nm technology as it is struggling with ‘tool and yield’ problems, according to analysts that have been surveyed by EE Times. Also, with the A17 Bionic and M3, TSMC will have varying wafer sizes, with a different number of chips per wafer, which will make mass production even more problematic.
According to Arete Research analyst Brett Simpson, with the A17 Bionic, TSMC will reportedly perform an 82-mask layer with a die size in the 100-110mm square range, resulting in 620 chips per wafer. As for the M3 that will be found in future Macs and iPad Pro models, this SoC should have a 135-150mm square die size, equaling 450 chips per wafer. At this time, TSMC’s yield rate is around 55 percent, but it should increase to 70 percent in the future.
Sadly, with 3nm chips, the biggest hurdle for TSMC’s foundry is ensuring that costly tooling equipment from various vendors perform at their optimum capacity, which does not appear to be the case here, hence the lowered efficiency. Earlier, Apple was rumored to have reduced the performance target of the A17 Bionic that will exclusively be found in the iPhone 15 Pro and iPhone 15 Pro Max, and the primary reason was TSMC’s struggles with 3nm chip production.
Simpson also states that TSMC’s primary goal is to optimize yields are wafer cycle times, both of which will improve
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