RISC-V Chiplet CPU With 432 Cores To Handle AI & HPC Workloads In Space
The European Space Agency has teamed with researchers at the University of Bologna and ETH Zürich to collaborate on a new RISC-V CPU to increase computational power while in space. The announcement was made during April 2023's Design, Automation, and Test in Europe Conference.
The newly formed project group called the Parallel Ultra Low Power Platform has developed an open-source RISC-V silicon AI chip with tape-outs called Occamy. Occamy will be capable of performing high-performance calculations, increasing efficiency while lowering the time it would take to make these calculations previously.
The design of Occamy has been in development since April 20, 2021, with the first tape out being in July 2022. It features nearly 1B transistors on a 72mm^2, similar to the Sandy Bridge quad-core chip designed by Intel in 2011. The transistor area is placed upon a carrier PCB that measures 52.5 x 45 mm for Fan-Out mounting.
The development is part of the EuPilot program that creates proprietary CPUs to lower the necessity of purchasing chips from manufacturers such as ARM and other x86 chip manufacturers. What is unique about this project is that Occamy utilizes new and older technology in its design.
The memory tile features dual 16 GB HBM2E DRAMs developed by Micron and utilizes 2.5D integration. Since each Occamy dies produces 10 W of power consumption at speeds of 1000 MHz, two Occamy dies, including the HBM2E DRAMs, would increase the total power up to two times. The 32-bit RISC-V control chip maps the data and directs the information to AI cores on the Occamy chip. Occamy has been tested on a single AMD Xilinx Virtex UltraScale+ VCU1525 FPGAs and two Xilinx Virtex UltraScale+ HBMs.
The design of the RISC-V "Occamy" CPU is
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