AMD Zen 5 Core Architecture Breakdown At Hot Chips: Zen For A New Chapter In High-Performance Computing
At Hot Chips, AMD is offering an in-depth look at its brand-new Zen 5 core architecture which will be powering its next high-performance PC journey.
A In-Depth Look At The Zen 5 Core Architecture: AMD's Next-Gen High-Performance Computing Architecture
AMD's Zen 1 core architecture first launched back in 2017 and since then, the company has introduced five new architectures (Zen+, Zen 2, Zen 3, Zen 4, Zen 5). AMD started the decade, by launching the Zen 3 architecture which brought a 19% IPC improvement to the table, an 8-core complex, and increased L3 caches per CCX while utilizing the 7nm/6nm process technologies.
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The company followed up with the Zen 4 release, bringing another 14% IPC improvement, AVX-512 (FP-256) instructions, doubling the L2 cache to 1 MB, support for VNNI/BFLOAT16 and rocking the 5nm and 4nm process technology.
This year, AMD introduced Zen 5, its latest high-performance core architecture which brings a 16% IPC uplift with AVX-512 and FP-512 variants, 8-wide dispatch, 6 ALUs, Dual pipe fetch/decode, and a 4nm/3nm technology utilization. Today, AMD is deep-diving into the full architecture for its Zen 5 at Hot Chips.
AMD starts by stating the design objectives for Zen 5. In terms of performance, Zen 5 aims to deliver another major 1T and NT performance increase, balanced cross-core 1T/NT instruction and data throughput, create front-end parallelism, increase execution parallelism, high throughput, efficient data movement and prefetching, and support AVX512/FP512 data paths for throughput and AI uplifts. Simultaneously, AMD wants to add new capabilities such as additional ISA extensions and new security features along with expanded platform support with its Zen 5 and Zen 5C core variants.
Following is an overview of AMD's Zen 5 core architecture:
2 Threads/Core
NextGen Branch Predictor
Caches:
- I-Cache:
