Intel Lunar Lake CPU Architecture Deep-Dive: Lion Cove +14% IPC, Skymont IPC More Than Raptor Cove, Next-Gen Power Managment & Scheduling

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Intel has introduced Lunar Lake, its most advanced, efficient & ground-breaking SOC to date and we are doing a deep dive into its P-Core & E-Core architectures and more.

Intel Lunar Lake Is A Ground-Breaking SOC, Powered By Lion Cove P-Core & Skymont E-Core Architectures, Which Bring Big Double Digit IPC Gains, Here's Our Full Deep-Dive

Lunar Lake has been the talk of the town ever since it was first unveiled by Intel and today, the company is finally taking the wraps off the chip to help us understand what makes it tick. The design goals for the Lunar Lake CPU were simple, to make a highly-efficient SOC which is designed to cater to the next-gen AI PC platforms such as Microsoft Copilot+. Some of the achievements of Lunar Lake include:

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• Breakthrough x86 power efficiency
• Exceptional Core Performance
• Massive Leap in Graphics
• Unmatched AI Compute

So before we get into the in-depth details, let's take a quick overview of Intel's Lunar Lake. It all begins at the construction which includes several packaging technologies housing several tiles.

The Lunar Lake SOC has 7 main components which start at the interposer package. This package hosts the memory, stiffener and the Base Tile which uses Foveros interconnect to combine the compute tile and Platform Controller Tile together. Also, you might notice that Intel went with way fewer Tiles on Lunar Lake versus Meteor Lake. That's done to achieve maximum efficiency and low latency overhead. As for process nodes, the Lunar Lake Compute Tile is made on TSMC's N3B and the Platform Controller die uses the TSMC N6 process node.

Lunar Lake is also Intel's first chip to feature on-package memory which comes in 16 GB & 32 GB (dual-rank) LPDDR5X configurations, running at up to 8533 MT/s speeds per chip. The memory supports a 16b x4 channel and achieves 40% lower PHY power along with a 250 mm2 area savings