Intel Arrow Lake-H CPUs For Laptops To Feature Core Architecture Trio: Lion Cove P-Cores, Skymont E-Cores, Crestmont LP-E Cores

wccftech.com:

Intel's Arrow Lake-H CPUs are now confirmed to include three different core architectures, Lion Cove P, Skymont E & Crestmont LP-E cores.

Intel Core Ultra 200 "Arrow Lake-H" For Laptops Are The Most Hybrid(est) of Them All, Three Unique Architectures In Lion Cove P-Cores, Skymont E-Core & Crestmont LP-E Cores

Intel is preparing to launch its desktop Arrow Lake-S "Core Ultra 200" CPUs in October but it will follow with the mobile variants close to CES 2025 since the family scales from desktops to mobile platforms. As we get closer to the launch of these CPUs, Intel is making preparations for the new lineup. Recent Linux PMU patches for Arrow Lake CPUs reveal new information about the mobile lineup, specifically the Arrow Lake-H variant as follows:

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The patch indicates that the Arrow Lake-H CPUs are going to have a mix of Skymont and Crestmont architectures for its Efficient cores, unlike the previous-gen Alder, Raptor, and Raptor Lake refresh chips, where you would usually see only one type of Efficient cores. With Meteor Lake, we did see Intel utilize LP-E cores but those were based on the same E-Core architecture whereas the Arrow Lake-H CPUs will deploy different E-core architectures for different purposes. The Skymont E-Cores will sit alongside the Lion Cove P-Cores on the main compute tile while the Crestmont LP-E cores will be featured on the SOC tile. The information confirms previous reports from a year back.

Keep in mind that Arrow Lake-H isn't the only lineup for Arrow Lake mobile chips. We also have the Arrow Lake HX & Arrow Lake U for high-performance and power-efficient laptops respectively. The Arrow Lake H series is built for mainstream gaming notebooks, featuring up to 6 Lion Cove P-cores and 8 Skymont E-cores. There will also be 2 Crestmont LP-E cores. At the moment, the code is under review but once it's ready, it could be merged with Linux Kernel v6.12. The HX chips will be configured like