AMD's Zen 5 chips will reportedly hit mass production at TSMC in the summer

pcgamer.com:

We all love a good architecture or two in the PCG hardware office and we especially like AMD's current Zen 4 and 4c designs. They're super efficient, clock really high, and their performance in games is spot on. So a report that the chip giant's next generation of designs will be hitting mass production toward the end of summer 2024 has piqued our interest and it'll be good news for games if that's the case.

There's no official announcement, of course, as AMD itself has been rather tight-lipped about Zen 5 but early snippets have suggested that the performance improvements are rather noteworthy. The rumour about the chips being ready around the end of summer stems from a report by technology outlet UDN (via Wccftech), that says 'the most critical core computing chip is manufactured by TSMC using the 3nm process' (Google translate).

This may be a typo or misunderstanding, as it has generally been rumoured that AMD will use TSMC's N4 process node for Zen 5. One possible explanation is that the 3nm production line, aka N3, will be used for the server-focused Zen 5c chips instead. I think we can assume that Zen 5c will be exactly like Zen 4c, in that it performs just the same as the normal architecture does, but the more compact layout limits its maximum clock speed.

That's fine for the server market, where all you want is as many cores and threads as possible, in the smallest chip possible. Making it on a 3nm node will mean the next generation of EPYC processors will be as compact and core-heavy as they possibly can, though I have no doubt they'll be fiercely expensive.

For PC gamers, even if the normal Zen 5 chips are made on the N4 lines, it will still be better than the current N5 chiplets that power the Ryzen 7000-series. How much better? Well, a recent update to AMD's GCC compiler suggests the Zen 5 core will sport more integer, addressing, and floating point pipelines, all of which means more instructions can be processed per clock cycle.

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