Taiwan Semiconductor Manufacturing Co. (TSMC) has officially announced its 2nm class process node. It’s set to ship to customers in 2025. The company also revealed more details regarding its 3nm technology, which is due to begin production later this year.
TSMC held its North America Technology Symposium(opens in new tab) on June 16th. It talked about its advanced technologies, including updates on its various processes and packaging tech. It also outlined its future expansion plans. The highlight for PC enthusiasts was undoubtedly the reveal of its 2nm node—referred to as N2—which includes a shift away from well established FinFET technology to a nanosheet transistor architecture. We can expect to see this tech in our computers in the coming years.
TSMC’s nanosheet technology uses what are known as GAAFETs (gate-all-around field-effect transistors). The aim is to reduce quantum tunnelling effects and leakage, which is a major barrier to further FinFETs scaling. With GAAFETs, these effects are greatly reduced, and Moore’s Law might have some last gasps.
N2 delivers the gains you’d expect to see from a process shrink, including 10-15 per cent higher performance at the same power or a 25-30 per cent lower power consumption at the same frequency and transistor count when compared to TSMC's N3 node.
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It’s important to note that node naming schemes are becoming less and less relevant. The move to a smaller node implies smaller transistors and greater
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