Possible Intel Arrow Lake-S Desktop CPU Die Layout Revealed, Rearranged Lion Cove P-Cores & Skymont E-Cores
Intel's Arrow Lake-S Desktop CPU's possible die layout has been revealed, giving us a first look at the restructured P-Core & E-Core arrangement.
Intel's Arrow Lake-S Desktop CPU Dies To Feature A Vastly Rearranged Core Structure, Lion Cove P-Cores & Skymont E-Core Clusters Packed Tightly Together
It looks like Intel is making a lot of changes to the internal structure of its next-generation Arrow Lake CPUs. According to a block diagram shared by @Kepler_L2, it looks like the P-Cores and the E-Cores will be arranged tightly this time.
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Starting with the details, the diagram is based on information that was revealed almost a year ago and earlier this year, a possible render was brought up by Kepler which was followed up by Bionic Squash who stated that the compute tile would look a lot like the new layout. The Arrow Lake CPUs will feature up to 8 P-Cores based on the Lion Cove core architecture and 16 E-Cores based on the Skymont E-Core architecture. This will enable up to 24 cores and 24 threads since the CPUs are said to lack hyper-threading support.
The Intel Lion Cove P-Cores for Lunar Lake CPUs feature 2.5 MB L2 per core but Arrow Lake CPUs will feature 3.0 MB L2 cache per core and 3 MB of L3 cache for a total of 24 MB L3 that will be fully shared while the Skymont E-Cores will feature 4 MB of L2 cache per cluster and each cluster will be getting 3 MB of L3 cache.
- Arrow Lake P-Core Cache (Lion Cove): 3 MB L2 / 3 MB L3
- Arrow Lake E-Core Cache (Skymont): 4 MB L2 / 3 MB L3
- Raptor Lake P-Core Cache (Raptor Cove): 2 MB L2 / 3 MB L3
- Raptor Lake E-Core Cache (Gracemont): 4 MB L2 / 3 MB L3
The interesting part is that each two Lion Cove P-Cores will have an E-Core cluster stacked right in the middle & they won't be separated from the P-Cores like in previous designs. This new layout might help in improving the inter-chip communication which can
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