Intel 5th Gen Xeon “Emerald Rapids” CPUs Detailed: Up To 40% Faster Than Sapphire Rapids, Die-Shot Pictured

wccftech.com:

A brand new Intel 5th Gen Xeon "Emerald Rapids" slide deck has emerged which gives us a bit more information on the chip layout and performance of the next-gen data center CPUs.

The slides come from an Intel "Data-Centric Processor Roadmap" presentation which was spotted by @InstLatX64. The deck looks very unfinished since it's missing several key data points but we do get to learn some additional information on the 5th Gen Xeon lineup which is codenamed Emerald Rapids.

So starting with the details, we first have our first close-up die shot of the 5th Gen Intel Xeon CPU which details its various architectural blocks. The Emerald Rapids CPUs are based on the P-Core architecture under the Raptor Cove ISA. The flagship chip, Xeon 8592+, incorporates a total of 64 cores, 128 threads, and a massive 480 MB L3 cache pool. As you can see, Intel has gone from a 4-tile design in 4th Gen Sapphire Rapids to a 2-tile design in 5th Gen Emerald Rapids CPUs.

Each chiplet is connected through a modular die fabric which sits between the two core and cache arrays. Each array features a total of 35 cores of which 3 cores are disabled per die. Each tile has 2 memory controllers supporting DDR5 DIMMs with up to 5600 MT/s speeds, three PCIe controllers (6 total), 2 UPI (4 total), and two accelerator engines (4 total). According to Intel, the Intel Emerald Rapids CPUs will offer:

Some of the features to expect within the 5th Gen Xeon "Emerald Rapids" CPUs include:

The Accelerator Engines embedded within the 5th Gen Xeon "Emerald Rapids" CPUs offer the latest AMX (Advanced Matrix Extensions) which are backed by a solid suite of AI software that utilizes optimized open-source frameworks and tools. Intel also claims that the next-gen Xeon chips will