AMD talks about its upcoming 3D V-Cache design at ISSCC

pcgamer.com:

AMD has teased its 3D V-Cache technology for several months, culminating in the reveal of the Ryzen 7 5800X3D at the company’s CES 2022 keynote back in early January. Fast forward to today, and AMD has revealed some further technical details behind its design at the International Solid-State Circuits Conference (via Hardwareluxx).

The AMD Ryzen 7 5800X3D is set to be the first consumer-level processor to include an additional stacked cache. It's bleeding edge stuff.

Each Zen 3 chiplet contains 32MB of L3 cache which is shared among all of the eight on-die cores. During the planning phase of Zen 3, AMD designed it so that extra cache could be stacked without a fundamental redesign, not unlike building a single story house with the structural integrity to add a second story relatively simply.

A Zen 3 chiplet with its integrated 32MB of L3 cache can be expanded up to 96MB, by adding 64MB of stacked SRAM. The stacked cache chip measures just 41mm² and is attached via copper bonding, therefore skipping the more complicated step of requiring soldering.

The 3D V-Cache is made up of multiple 8 MB «slices» with 1024 contact points for each slice. Eight such slices mean there are 8192 contact points between the V-Cache and the underlying CCD. This delivers a bandwidth of beyond 2 TB/s which is partucularly impressive given the cache is not on the die itself.

AMD has had to tweak the underlying chiplets in order to fit the extra Z height inside the same form factor as a regular 5000 series CPU. AMD has also had to thin the CCDs and make tweaks to cater for the increased thermal dissipation that's to be expected from a stacked design.

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