PCI Special Interest Group (PCI-SIG) unveils draft specifications version 0.3 of PCIe Express 7.0, opening new doorways in the technology. The company will update more on the technology at its annual developer conference being held in Santa Clara.
PCIe Express 7.0 is set to feature speeds yet to be seen in the industry. It is expected to include speeds of up to 128 GT/s per pin, a substantial improvement from previous generations. It will feature double the bandwidth for PCIe devices featuring 16GB/s of full-duplex, bidirectional bandwidth, which is a significant increase since PCIe 6.0 comes with 8GB/s.
The new version 0.3 draft is set to be provided to various board members. This is the first step towards making the technology more widely accessible. The draft lets consumers and group members know about the potential of PCIe Express 7.0 hence garnering interest.
The new technology will feature PAM4 signaling and 1b/1b flit mode encoding, similar to what we saw in PCIe 6.0. The main changes are in the physical layer development, resulting in improved performance. PCI-SIG has set a timeframe for PCIe 7.0 to achieve complete development. The company expects the technology to go live by 2025 after initial testing and development are completed. Moreover, PCI-SIG has also disclosed information about the compliance program, which is certification for large-scale industries. Here is what the company has to say about it.
A compliance program for the specification, in turn, should be up and running in 2027. The compliance programs are the functional barometer for hardware availability, as compliance testing and certification is effectively necessary before any large-scale commercial hardware using the new spec can ship. And with few
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