Intel AVX10 ISA To Feature AVX-512 Instructions With Support on Both P-Cores & E-Cores

wccftech.com:

Intel's upcoming AVX10 ISA (Instruction Set Architecture) has been detailed and comes with AVX-512 support for both P-Cores & E-Cores.

In a slide published by Twitterati, Longhorn, we get to see details of Intel's upcoming AVX10 ISA that seems to be coming in two versions, a pre-enablement (AVX10.1) and a post-enablement (AVX10.2). Both ISAs have one major addition which is support for optional 512-bit FP/int which is something that was excluded from recent client chips. The Intel AVX-512 ISA has been around for a while with Rocket Lake and Tiger Lake but the company decided to disable it from the most recent client-tier chips such as Alder Lake and Raptor Lake.

But it looks like Intel might be bringing these instructions back with processors that support the AVX 10 ISA. According to the pre and post-enablement details, the AVX10 ISA is part of the latest APX (Advanced Performance Extensions) and will offer:

Now it's not like AVX-512 has entirely disappeared. The support for the instructions still exists on the HPC side with the Xeon chips. However, the client side might just bring AVX-512 instructions back since AMD is already offering it on its Ryzen 7000 consumer processors and they have shown some impressive performance capabilities in specific workloads without taking a big hit on power consumption. Power consumption was a major concern with Intel's previous AVX-512 instructions.

Intel AVX10 represents a major shift to supporting a high-performance vector ISA across future Intel processors. It allows the developer to maintain a single code-path that achieves high performance across all Intel platforms with the minimum of overhead checking for feature support. Future development of the Intel AVX10 ISA will continue to