AMD Strix Point Halo “GFX1151” & Strix Point “GFX1150” APUs Spotted In ROCm, RDNA 3.5 iGPU Confirmed
AMD's next-gen Strix Point APUs including the Halo variant have been spotted with RDNA 3.5 iGPUs in the ROCm Github repository.
AMD RDNA 3.5 GPUs To Be Featured On Next-Gen Strix Point & Strix Point Halo "Ryzen" APUs
Although the listings of the RDNA 3.5 "GFX1150" and "GFX1151" IDs are nothing new since we have been seeing them in various patches on Linux and the AMDGPU LLVM backend, what's new here is that this is the first time that Strix Point and Strix Point Halo are mentioned along with a respective GPU ID that they would utilize on launch.
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The latest commit within ROCm Github, titled "Strix Halo Support and Strix support in staging", is clear enough that more robust support is being added to the framework. Once again, AMD's Strix Point Halo APUs will be utilizing the GFX1151 IP while the Strix Point 1 APUs will be utilizing a GFX-1150 IP. The difference between the current GFX110X and the upcoming GFX115X IPs is that these new ones feature the refreshed and slightly more optimized RDNA 3.5 GPU architecture which will enable higher clocks and more cores on the premium parts along with some efficiency uplifts.
The first AMD Strix Point APUs will appear later this year under the Ryzen 8050 APU branding and are expected to feature a next-gen XDNA 2 NPU "Ryzen AI" with up to 3x the performance uplift so that's around 48 TOPs coming from the NPU alone and over 60 TOPs when combined with the GPU and CPU. The AMD Strix Point standard SKUs are expected to feature up to 12 Zen 5 CPU cores and 16 RDNA 3.5 GPU cores while the Strix Point Halo APUs are expected to feature up to 16 Zen 5 CPU cores and up to 40 RDNA 3.5 GPU cores.
AMD Ryzen 8050 Strix Point Mono Expected Features:
- Zen 5 (4nm) Monolithic Design
- Up To 12 Cores In Hybrid Config (Zen 5 + Zen 5C)
- 32 MB of Shared L3 cache
- 16 RDNA 3+ Compute Units
- 128-bit LPDDR5X Memory Controller
- XDNA 2
