AMD Zen 5 & Zen 5C EPYC CPU Rumors: Turin With 16 CCDs 128 Cores, Turin-Dense With 12 CCDs 192 Cores, Turin-X With 1.5 GB L3 Cache
New rumors of AMD's Zen 5 & Zen 5C EPYC CPU family, codenamed Turin, have leaked out which point out up to 16 CCDs & 192 cores.
The latest rumors come from Weibo leaker, 剧毒术士马文, who seems to have acquired an internal AMD roadmap that reveals several next-generation Turin designs based on the Zen 5 and Zen 5C core architecture. Most of this information had already been talked about by Moore's Law is Dead but we get to learn a few more details such as the max cache counts and the CCD configurations.
AMD EPYC Turin & Turn-X With Zen 5: Up To 128 Cores, 4nm Process
Starting with the first family, we have the AMD EPYC Turin (Classic) which will stick with the chiplet design and house up to 128 cores, 256 threads, and TDPs of up to 500W which can be configurable on certain SKUs up to 600W (as revealed in today's Gigabyte leak). In a previous leak, it was shown that the EPYC Turin chips would feature the same L2 and L3 cache as Zen 4 with a small upgrade to the L1 cache.
Since these chips are packaged on a 4nm process node, that will lead to a smaller die area per core, allowing AMD to cram up to 16 CCDs within the same package that retains its socket compatibility with SP5 platforms.
Moving on, we have the AMD EPYC Turin-X chips which will be outfitted with a 3D V-Cache. These chips will retain the 64MB of 3D V-Cache per CCD which totals 1024 MB across the 16 CCDs & 512 MB of standard L3 cache. Totaling up to 1536 MB or 1.5 GB of L3 cache. If we combine the L2 cache which is 1 MB per core or 128 MB in total, that increases to 1664 MB of total cache which is still not including the L1 cache. That's a 33% higher cache compared to the upcoming Genoa-X CPU family.
AMD EPYC Turin Dense & Turin AI With Zen 5C: Up To 192 Cores, 3nm
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